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Chapter 1: About This MegaCore Function
Performance and Resource Utilization
1–7
■
■
■
Arria V GZ (5AGZME1H2F35C3)
Cyclone V (5CGXFC7C6F23C6)
Stratix V (5SGXMA7H2F35C2)
Table 1–3. RapidIO IP Core FPGA Resource Utilization I
Parameters
Registers
Memory
Device
Arria V GX
Variation
Physical layer only
Physical and
Transport layers,
and
I/O master and
slave
Mode
1x
2x
4x
1x
2x
4x
Baud Rate
(Gbaud)
5.00
3.125
5.00
3.125
ALMs
4300
4600
4300
5300
7400
7000
Primary
6000
6100
6000
7100
10000
9800
Secondary
336
413
352
540
654
621
Blocks
(M10K or
M20K (1) )
35
35
35
56
59
59
1x
2800
3800
263
29
Physical layer only
2x
4x
4700
4400
6100
6000
482
440
27
27
Arria V GZ
Cyclone V GX
Physical and
Transport layers,
and
I/O master and
slave
Physical layer only
Physical and
Transport layers,
and
I/O master and
slave
1x
2x
4x
1x
2x
4x
1x
2x
4x
5.00
3.125
2.5
3.125
2.5
5700
7600
7200
2900
4600
4300
5300
7100
6700
7300
10000
9900
3700
5800
5600
7100
9400
9300
570
797
782
276
399
357
570
687
580
36
39
43
35
35
35
58
59
59
1x
2700
3900
300
24
Physical layer only
2x
4x
4700
4500
6100
6000
491
427
20
22
Stratix V GX
Physical and
Transport layers,
and
I/O master and
slave
1x
2x
4x
5.00
5700
7700
7200
7300
10200
9900
585
777
828
36
33
44
Note to Table 1–3 :
(1) M10K for Arria V and Cyclone V devices and M20K for Arria V GZ and Stratix V devices.
May 2013
Altera Corporation
RapidIO MegaCore Function
User Guide
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